The present invention relates to a semiconductor device having a recessed electrode structure and, more particularly, to a field effect transistor having a recessed gate electrode structure and a method of producing the same.
With the recent development of superhigh precision crystal growth techniques such as the MBE (Molecular Beam Epitaxy) and the MOCVD (Metal Organic Chemical Vapor Deposition), realization of superhigh speed devices (e.g., that disclosed in the specification of Japanese Patent Laid-Open No. 132074/1980) utilizing a gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) hetero junction is under way. Since an excellent insulating material for a GaAs/AlGaAs hetero junction has not yet to be found, Schottky junctions formed by metals and compound semiconductors are employed to constitute gate structures for various kinds of field effect transistor (FET).
FIG. 1 is a cross-sectional view of a selectively doped hetero junction FET as one example of the above-described conventional FETs. In the figure, the reference numeral 100 denotes a semi-insulating GaAs substrate, 11 an undoped GaAs layer, 12 an undoped AlGaAs layer (not intentionally containing any impurity, and in many cases, resulting in an n.sup.- -type layer having an impurity concentration of 10.sup.15 cm.sup.-3) known as a spacer, the layer 12 generally having a film thickness e of about 60 .ANG.. The numeral 13 denotes an n-type AlGaAs layer, and 14 an n-type GaAs layer. The total film thickness d of the AlGaAs layers 12 and 13 is generally about 500 .ANG.. The numeral 31 denotes a gate metal of an enhancement type FET (the threshold voltage V.sub.th : about 0.1 V), 30 a gate metal of a depletion type FET (the threshold voltage V.sub.th : about -0.8 V; the gate voltage V.sub.G =0 V at which the channel is open). Representing the doping level of the n-type AlGaAs layer 13 by N.sub.D for simple calculation, the threshold voltage V.sub.th may be given in the main term as follows: ##EQU1##
where .phi..sub.Bn represents the height of the Schottky barrier between the gate metal and the AlGaAs layer, .DELTA.E.sub.c the size of discontinuity of the conduction band edge between the GaAs layer 11 and the AlGaAs layer 12, q the unit charge, and .epsilon. the dielectric constant of AlGaAs. A critical consideration in improvement of such FETs in performance lies in lowering the parasitic resistance R.sub.sg of the gap between the source 32 and the gate 30 and that between the source 34 and the gate 31. The parasitic resistance R.sub.sg is generally represented as follows: ##EQU2##
where L.sub.sg represents the distance between the source and the gate, w the width of the transistor, .gamma..sub.c the contact resistance of the source electrode, and .rho..sub.s the carrier sheet resistance of the portion between the source and the gate. The minimum source-gate distance L.sub.sg which can be obtained by the use of photolithography or electron beam lithography is generally about 0.5 to about 0.8 .mu.m. The sheet resistance .rho..sub.s is about 1 k.OMEGA./.quadrature. to 100 .OMEGA./.quadrature.. It is characteristic of FETs employing compound semiconductors to involve a considerably high sheet resistance .rho..sub.s (the sheet resistance of Si-MOSFETs is generally about 1 to about 5 .OMEGA./.quadrature.). This is mainly because the upper limit of the carrier density in compound semiconductors is relatively low, i.e., 2.times.10.sup.18 cm.sup.-3.
On the other hand, there have been known one type of GaAs MESFET (Metal-Semiconductor Field Effect Transistor) employing compound semiconductors such as gallium arsenide (GaAs) and another type of FET employing as an active layer a two-dimensional electron gas (2 DEG) formed at the hetero junction interface between aluminum gallium arsenide (AlGaAs) and GaAs (such FETs being known as 2 DEG-FETs). These FETs are employed as low-noise high-frequency FETs. FIG. 2 is a cross-sectional view of an FET of the type described above. An n.sup.+ -type GaAs layer 15 (the doping level: 2.times.10.sup.18 cm.sup.-3 ; the film thickness: about 2000 .ANG.) is formed for the purpose of lowering the parasitic resistance between the source and the gate. A gate electrode 30 is formed using a so-called recessed structure. Such recessed structure is generally formed using a chemical etching so as to have a depth of 3000 to 4000 .ANG., and a gap which generally has a size of 0.1 to 0.2 .mu.m and a sheet resistance of about 1 k.OMEGA./.quadrature. is formed between the n.sup.+ -type GaAs layer 15 and the gate electrode 30 as shown in FIG. 2, which results in an increase in the parasitic resistance.
In order to prevent such increase in the parasitic resistance, improved recessed structures have been proposed and carried out, such as that shown in FIG. 3 in which the gate metal 30 is self-aligned with the recess and that shown in FIG. 4 in which a side insulator film 5 is formed between the gate metal 30 and the n.sup.+ -type GaAs layer 15.
Low-noise high-frequency FETs of the type described above are described in, for example, "IEEE, ED 27 (1980), page 1029". In the above-described figures, the reference numeral 9 denotes an n-type GaAs active layer, 32 a source electrode, 33 a drain electrode, and 35 an overhang portion of the gate metal 30 overhanging the n.sup.+ -type GaAs layer 15. The broken line below the n-type GaAs active layer represents the boundary between the substrate and the active layer.
The prior arts shown in FIGS. 3 and 4 are effective in lowering the parasitic resistance. However, in the self-alignment process with respect to a recess such as that shown in FIG. 3, the gate metal 30 is in direct contact with the n.sup.+ -type GaAs layer 15, and the source-gate breakdown voltage (the voltage at which a leakage current flows when the source and the gate are reverse-biased) is about 1.5 to about 3.0 V, which is far lower than a practical level, i.e., 7 to 10 V, disadvantageously. On the other hand, the structure, in which the insulator 5 is formed between the gate metal 30 and the n.sup.+ -type GaAs layer 15 in order to prevent deterioration of the source-gate breakdown voltage, involves the problem that the gate metal 30 which overhangs the n.sup.+ -type GaAs layer 15 (see a portion of the gate metal denoted by the reference numeral 35) substantially doubles the gate capacitance.
In an FET having the structure shown in FIG. 2, even if the n.sup.+ -type GaAs layer 15 is formed thick, the sheet resistance .rho..sub.s between the source and the gate is about 100 .OMEGA./.quadrature..
The contact resistance .gamma..sub.c of the source electrode is about 0.2 .OMEGA.mm, and the lower limit thereof is given by the fact that the doping level of the n.sup.+ -type GaAs layer which is in contact with the source and drain electrode metals is 2.times.10.sup.18 cm.sup.-3. If the sheet resistance .rho..sub.s is lowered to several .OMEGA./.quadrature. or less and the contact resistance .gamma..sub.c is lowered to 0.02 .OMEGA.mm or less, it is possible to expect a great improvement in performance of the FETs.
In the above-described prior arts, the parasitic resistance is increased mainly because the distance L.sub.sg between the source and the gate is 0.5 .mu.m or more and a portion of the semiconductor which defines the gap between the source and gate has a sheet resistance of about 100 .OMEGA./.quadrature..